1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, relates to a semiconductor memory device which is capable of exchanging data in a serial fashion between the device and the exterior while internally exchanging data with memory cells in a parallel manner, in order to realize high speed operations.
This application is based on Japanese patent application No. Hei 11-104623, the content of which is incorporated herein by reference.
2. Description of Related Art
In recent years, in concert with the dramatic advances in the performance of memory devices which have a large capacity and which are moreover capable of high speed operation. Examples of semiconductor memory devices having satisfactorily large capacity include, for example, DRAM (dynamic random access memory). DRAM conducts reading and writing of data by charging and discharging capacities within memory cells, so that it is impossible to force the operations within DRAM to follow at the speeds of system buses or microprocessors, which operate in accordance with high speed clock signals of a few hundred MHz or more. For this reason, structures have recently come to be adopted for DRAM in which the entirety of a memory cell array is divided into a plurality of banks which are mutually independent memory units, and access is conducted in order to differing banks while operating these banks in parallel. By doing this, it is possible to lower the internal DRAM data writing with respect to the external data writing while maintaining, from the point of view of the exterior of the DRAM, the appearance of data writing which matches the operational speed of the microprocessor.
In addition, strategies have been applied to lower the data writing within the DRAM with respect to the external data writing by sending and receiving data in a serial manner when data is exchanged between the DRAM and the exterior, while conducting data reading and writing among memory cell arrays within the DRAM in a parallel manner. The reason for this is that when data are selected within the memory cell arrays, it becomes difficult to conduct the adjustment of the timing between bits. For this reason, when data readout is conducted from a DRAM, parallel data comprising a plurality of bits are simultaneously read out from the memory cell arrays, these are converted to serial data, and are sequentially outputted to the exterior.
For example, by exchanging the 8-bit parallel data used internally with the exterior of the DRAM one bit at a time in a serial fashion, it is possible to reduce the data writing within the DRAM to 1/8 that in the exterior of the DRAM. Accordingly, in a DRAM with such a structure, a serial to parallel converter circuit and a parallel to serial converter circuit, are provided in order to interconvert the serial data which are exchanged with the exterior and the parallel data which are internally processed. Hereinbelow, the serial to parallel conversion will referred to as the serial-parallel conversion, and the parallel to serial conversion will be referred to as the parallel-serial conversion.
The structure of a semiconductor memory circuit such as that described above is shown in the block diagram of FIG. 13. In order to facilitate the explanation, this diagram shows, in an overlapping fashion, the structure of a semiconductor memory device containing four memory cell arrays 1-1 through 1-4, which has a 128 megabit capacity, and the structure of a semiconductor memory device containing eight memory cell arrays 1-1 through 1-8, which has a capacity of 256 megabits. Accordingly, the memory cell arrays 1-5 through 1-8 and the serial-parallel/parallel-serial conversion circuits 3-5 through 3-8 (described hereinafter) are not present in the 128 megabit semiconductor memory device. The structure of the 128 megabit device is that which is conventionally employed, and the structure of the 256 megabit device simply represents an increase in capacity over that of the 128 megabit device.
In the figure, interface logic 2 includes, in addition to an input/output (I/O) interface circuit which serves to conduct data transfer between the semiconductor memory devices depicted in the figure and the exterior, a booster circuit which is provided with common DRAM, a fuse for redundancy, a substrate generating circuit, and the like. Furthermore, serial-parallel/parallel-serial conversion circuits 3-1 through 3-8, which have the same structure, are provided between each memory cell array 1-1 through 1-8 and interface logic 2, respectively, as circuits which correspond to the serial-parallel conversion circuit and the parallel-serial conversion circuit described above. For example the serial-parallel/parallel-serial conversion circuit 3-1 conducts readout and writing using parallel data with respect to the corresponding memory cell array 1-1, and conducts the exchange of serial data with the exterior via interface logic 2.
That is to say, serial-parallel/parallel-serial conversion circuit 3-1 has the function of converting parallel data successively read out from memory cell array 1-1 to serial data and outputting these to interface logic 2, and has the function of converting serial data supplied from interface logic 2 to parallel data and writing these simultaneously into memory cell array 1-1. Examples of semiconductor memory devices which are provided with such serial-parallel/parallel-serial conversion circuits include, for example, cache memories and field memories, which are memories for image processing which have a FIFO (first in first out) function, as well as video RAM which stores the data of displayed images.
Here, FIG. 14 shows the connection relationships between the serial-parallel/parallel-serial conversion circuits 3-5 and 3-1 depicted in FIG. 13 and the input and output interface circuit 5-1 which is within the interface logic 2 depicted in Figure 13. Here, the depiction centers on the data flow, and the concrete structure of the serial-parallel/parallel-serial conversion circuits is not depicted. In the Figure, the DQ0 serial through DQ7 serial are groups of 8 bit data which are inputted and outputted simultaneously between the semiconductor memory device and the exterior via the input and output interface circuit 5-1. As will be shown hereinafter in the embodiments of the present invention, the writing and reading of the DQ0 serial through DQ7 serial depicted in FIG. 14 are separate; however, so as to avoid complexity, the reading and writing functions are depicted together in a single signal line.
Furthermore, the DQ0 parallel through DQ3 parallel are eight-bit four-group data which are simultaneously inputted and outputted with the memory cell array 1-5 depicted in FIG. 13. In the same way, the DQ4 parallel through DQ7 parallel are eight-bit four-group data which are simultaneously inputted and outputted with the memory cell array 1-1 depicted in FIG. 13. Next, references 4-0 through 4-7 indicate shift registers which conduct the shift operation in a synchronous manner with the clock signal CLOCK; these all have the same structure. Furthermore, the data load signal LOAD serves to indicate the timing for the loading of data into these shift registers. The clock signal CLOCK and the data load signal LOAD are supplied to the shift registers described above at each stage; however, so as to avoid complexity, these connection relationships are not depicted. In FIG. 14, the DQ0 serial through DQ7 serial are depicted in such a way as to be connected to the bit 0 of the corresponding shift register; this indicates only that in the case of reading or writing with respect to the memory cell array, the 0th bit is initially processed, so that either the data of bit 0 are initially outputted from each shift register, or the data of bit 0 are initially applied to each register.
Shift registers 4-0 through 4-7 are disposed for each I/O pad (DQ0-DQ7). When readout is to be conducted from the memory cell array, each shift register loads 8-bit parallel data at the point in time at which the data load signal LOAD becomes effective, and after this, conduct shifting of the parallel data one bit at a time in a manner synchronous with the clock signal CLOCK, so that the 8-bit serial data is sent to input/output interface circuit 5-1 from bit 0 through bit 7. On the other hand, when writing is to be conducted with respect to the memory cell array, the serial data are supplied in order from bit 0 to bit 7 from the input/output interface circuit 5-1 to each shift register, so that each shift register incorporates the serial data inputted in a synchronous manner with clock signal CLOCK, and ultimately outputs 8-bit parallel data. Furthermore, input/output interface circuit 5-1 is the part within the semiconductor memory device which is required for the highest speed operation; it controls the exchange of serial data between each shift register and the exterior.
As described above, in conventional semiconductor memory devices, the serial-parallel/parallel-serial conversion circuits are disposed so as to enclose the interface logic 2 (FIG. 13), and a number of serial-parallel/parallel-serial conversion circuits is required which corresponds to the number of memory cell arrays. Accordingly, when an increase in capacity is made from the 128-megabit DRAM indicated by the dashed line in FIG. 13 to a 256 -megabit DRAM, the number of memory cell arrays goes from four to eight, and in proportion to this, the number of serial-parallel/parallel-serial conversion circuits also increases. As a result, the circuitry increases in area by that surface area which is taken up by the serial-parallel/parallel-serial conversion circuits, and the surface area of the chip as a whole becomes larger. Furthermore, the load capacity and the like of the clock used to operate the serial-parallel/parallel-serial circuits also increases, so that the power consumption also increases.
In addition to these problems, in the conventional serial-parallel/parallel-serial conversion circuit structure, there is an important drawback which has a direct effect on the access time of the semiconductor memory device. This point will be explained with reference to FIG. 15. FIG. 15 shows the connection relationships between the memory cell arrays and the input/output pads in the semiconductor memory device depicted in FIG. 13 in greater detail; those structural elements which are identical to those depicted in FIGS. 13 and 14 are given identical reference numbers. As shown in the figure, the input/output interface circuit 5-1 depicted in FIG. 14, and an input/output interface circuit 5-2 having the same structure, are provided within interface logic 2, and these are both disposed in the vicinity of the center of the chip.
Included in the input/output interface circuit are I/O pads for eight pins, I/O buffers corresponding to each I/O pad, circuitry for selecting either data from the memory cell arrays in the upper half (for example, memory 1-5) or data from memory cell arrays in the lower half (for example, memory cell array 1-7), and the like. The DQ0-DQ7 shown in input/output interface circuit 5-1 indicate I/O pads corresponding to serial data DQ0-DQ7 shown in FIG. 14. Furthermore, focusing on the memory cell arrays which are in the half upward from the interface logic 2, DQ0-DQ3 and DQ4-DQ7 are connected, respectively, to memory cell arrays 1-5 and 1-1 as described above, and furthermore, the DQ8-DQ11 and DQ12-DQ15 I/O pads are connected, respectively, to memory cell arrays 1-2 and 1-6. The memory cell arrays which are in the half below the interface logic 2 are identical.
Here, if one assumes that the semiconductor memory device has the structure of the 128 megabit structure shown by the dashed line in FIG. 13, no particular problems are present. In such a case, there are no serial-parallel/parallel-serial conversion circuits corresponding to memory cell arrays 1-5 through 1-8, and for example, serial-parallel/parallel-serial conversion circuit 3-1 is connected closely to the I/O pads (DQ0-DQ7) within input/output interface circuit 5-1. For this reason, even if the I/O pads are different, the length of the wiring between the serial-parallel/parallel-serial conversion circuits and the input/output interface circuits does not differ dramatically, so that there is not so much undesirable variation caused in the response time between these I/O pads.
However, when the capacity of the semiconductor memory device is expanded so as to achieve a structure of, for example, 256 megabits, the problems begin to become pronounced. In other words, whereas the I/O pads DQ4-DQ5 and the like were in close proximity to the serial-parallel/parallel-serial conversion circuit 3-1, so that wiring delays were small, the I/O pads DQ0-DQ3 and DQ6-DQ7 are distant from the serial-parallel/parallel-serial conversion circuit 3-5, so that the wiring delay becomes larger than that in the case of DQ4 and DQ5 by this amount. In this way, when the distance from the serial-parallel/parallel-serial conversion circuit to the I/O pad differs for each I/O pin, then the timing of the data, which should be simultaneously inputted and outputted, becomes disordered, and this becomes a great obstacle in increasing the speed of the semiconductor memory device.
As described above, when the number of memory cell arrays are increased in order to increase the capacity, the chip extends of necessity in the longitudinal direction of the interface logic 2 shown in FIG. 13, and the problems described above occur. These problems occur because the I/O pads arc disposed in the vicinity of the center of the chip, and it might be thought that by moving the I/O pads to positions in the vicinity of the memory cell arrays in concert with an increase in capacity so that, for example, the I/O pads of DQ0-DQ7 shown in FIG. 15 might be disposed equidistant from the memory cell arrays 1-5 and 1-1, the problem would be solved. However, the most recent packages are CSPs (chip size packages) having a size which takes into account the size of the chip. For this reason, for the reasons described above, irrespective of whether the number of I/O pads has not been changed, the disposition of the I/O pads cannot be easily changed.
FIG. 16 shows the bottom surface of a BGA (ball grid array) which is a type of CSP; this actually realizes a conventional semiconductor memory device which is provided with four memory cell arrays. Ball bumps are disposed in the form of a matrix in the package in BGA, and I/O pads are arranged in a concentrated manner in the vicinity of the center of the package. In other words, in the figure, the parts surrounded by circles (.smallcircle.) are ball bumps, and the rectangles (.quadrature.) which are smaller than the ball bumps are the pads. From left to right in the figure, "DQA7-DQA0, DQB0-DQB7" is written in the pads and in the circles (.smallcircle.) of the ball bumps corresponding thereto, and these correspond to the DQ0-DQ7 and DQ8-DQ 15 shown in FIG. 15. Even if the memory capacity is doubled and the number of memory cell arrays becomes eight, the position of the pads and balls will not change from that shown in FIG. 16; however, because the chip size will not be the same, the shape will be one in which the left and right edges in the figure are further extended in the left and right directions.
At this time, one reason for fixing the positions of the balls is that if the balls are moved in accordance with chip size, the wiring to the read frames becomes difficult. Accordingly, the position of the balls is of necessity fixed in the central portion of the chip. Another reason is that if the disposition of the balls is greatly changed when the memory capacity is increased, it becomes impossible to commonly employ the printed substrate on which design is conducted using the conventional ball arrangement as a model, and this will cause a problem in that it will be necessary to completely redesign the print substrate from the beginning. For these reasons, it is necessary to establish a ball arrangement which will, as much as possible, maintain the characteristics of the previous generation even after a new generation of semiconductor memory devices is developed, and this also matches the needs of the market.
Additionally, the following problems are also present in the conventional semiconductor memory device structure. As shown in FIG. 14, if shift registers 4-0 through 4-7 are arranged so as to correspond with the I/O pads (DQ0-DQ7), then the wiring which supplies the data load signal LOAD extends from the right side to the left side in the figure, and when the data load signal LOAD is distributed to shift registers 4-0 through 4-7, a transmission skew is produced. For this reason, the operational frequencies of the semiconductor memory device are limited. Furthermore, when the clock signal is wired in the same manner as the data load signal LOAD and distributed to each shift register, then an undesirable variation in the clock phase is produced between shift registers, and this has an effect on access.
In FIG. 14, clock signal CLOCK is caused to move in the left and right direction from the vicinity of the center of serial-parallel/parallel-serial conversion circuits 3-5 and 3-1 and is distributed to each shift register. When this is done, it is possible to make the apparent length half that in the case of wiring similar to that of data load signal LOAD; however, the fact that the clock is not transmitted to each shift register at the same time remains unchanged. Accordingly, a I/O skew is also produced in this case, and the operating margin is reduced, and this results in a limitation of the operational frequencies of the semiconductor memory device itself.
Furthermore, if the wiring shown in FIG. 14 is employed, a discrepancy is produced between the clock signal skew and the data load signal skew and this results in a disruption of high speed operations. Consideration could also be given to restricting the data load signal in the same manner as the clock signal; however, there is a limitation in wiring space and the like, and in practice it would be very difficult to restrict all the signals in the same way as the clock signal in the figure. As described above, it is important to restrict the wiring of the clock signal or the load signal and it is an objective to make the skew in these signals between I/Os as small as possible in order to realize high speed operations.